This invention relates to the fabrication of integrated circuits and, more particularly, to a method for protecting fuses from damage while at the same time increasing the fuse density (i.e., the number of fuses per unit area) when employing a laser beam to blow selected fuses forming a fuse bank.
Semiconductor integrated circuits (IC) and their manufacturing techniques are well known in the art. In typical integrated circuits, large number of semiconductor devices are fabricated on a silicon substrate. To achieve the desired functionality, a plurality of conductors are typically employed for coupling selected devices together. In some integrated circuits, some of the conductive links or wires may be coupled to fuses, which may be selectively programmed (i.e., blown) after fabrication using lasers. By way of example, in a dynamic random access memory (DRAM), fuses may be employed during manufacturing to protect from destruction some of the gate stacks of the transistors from inadvertent built-up charges. Once the fabrication of the IC is substantially complete, the fuses may be blown or cut to permit the DRAM circuit to function as if the protective current paths never existed. More commonly, fuses may be employed to set an enable bit and address bits of a redundant array element in a DRAM circuit or for repairing defects found in the DRAM by appropriate replacement of defective elements with redundancy replacement elements present within or without the chip.
To facilitate discussion, FIG. 1 illustrates a typical dynamic random access memory (DRAM) integrated circuit, including a main memory array 102. To allow the replacement of a defective main array element within main memory array 102, a redundancy replacement array 104 is provided as shown. A plurality of fuses in fuse array 106 are coupled to redundancy array 104 via a fuse latch array 108 and a fuse decoder circuit 110. In order to replace a defective main memory array element, individual fuses in fuse array 106 may be blown or cut by setting their values to either a binary 1 or 0 as dictated by the decoder circuit. During this operation, the values of the fuses in fuse array 106 are typically loaded into the fuse latch array 108 when power is turned on. These values are then decoded by fuse decoder circuit 110 during run time, thereby facilitating the replacement of selected defective memory array elements with specific redundancy elements which are part of the redundancy array 104. Techniques for replacing failed main memory array elements with redundant array elements are well known in the art and will not be discussed in great detail here for brevity sake.
As previously mentioned, the fuse links within fuse array 106 may be selectively blown or programmed with a laser beam. Once blown, the fuse changes from a highly conductive state to a highly resistive (i.e., non-conductive) state, since a programmed fuse inhibits current from flowing through it and represents an open circuit to the path taken by the current.
With reference to FIG. 2a, a fuse bank 200 is shown having a plurality of fuse links, such as 202, 204, 206, and 208, (represented in FIG. 1 as fuse array 106), are shown in their original unblown, i.e., conductive state.
In FIG. 2b, a laser beam has been employed to cut or blow fuse link 204, thereby inhibiting the flow of current therethrough. If the fuses are placed too closely together for a given laser wavelength and spot size, i.e., by deleting the fuse, an adjacent fuse link may inadvertently be blown or cut, rendering the IC defective or, at best, a possibility exists of causing damage to neighboring fuses during the fuse blow process. This is because the damage zone around a blown fuse is typically larger than the fuse itself in view of a number of factors, such as the laser spot size, thereby damaging the passivation layer over the fuses which extend outward from the fuses. Clearly many factors enter in determining the severity of the damage caused by laser beam, e.g., the amount of energy carried by the beam, its wavelength and the diameter of the beam.
In FIG. 3a, there is shown a typical fuse bank 300 consisting of fuses 302, 304, and 306. Additional structures, e.g., 308 and 310, are placed within the fuse bank and between the fuses. These structures, formed by barrier material, typically tungsten or molybdenum, act as crack stops when fuse 304 is blown by a laser beam (not shown). Further exhibited are cracks 320 propagating from fuse 304 and stopping at crack stop 308 and 310.
In another view of the same structure (FIG. 3b), a top view of the above structure built on a substrate 350 is illustrated. Only two fuses, i.e., 302 and 304, are exhibited. The crack stop is made up of several layers 330 through 340 which coincide with the several levels of wiring used in the fabrication process of the semiconductor chip. Once again, the cracks 320 are arrested by the crack stop, preferably made of portions of refractory metal.
Several other methods of protecting fuses have been advanced for protecting fuse elements to ensure that the fuse remains unaffected when the fuse blows open. In one example described in U.S. Pat. Nos. 5,420 455 and 5,523,253, both issued to Gilmour et al. on Mar. 31, 1994 and May 30, 1995, respectively, a deposition of metal having a melting point higher than the melting point of the fuses is interspersed between the fuses. Such metals include tungsten and molybdenum. These barriers are resistant to cracking and are designed to prevent any cracks from propagating to other adjacent fuses in the immediate neighborhood. The bodies of barrier material are positioned such that they extend from the top surface of the layer containing the fuse links to approximately half-way down to the mid-point of the thickness of the fuse link.
The structure described by Gilmour et al. suffers from a major drawback, in that it requires specialized metals, oftentimes undesired ones due to manufacturing process considerations and/or they suffer from unwanted characteristics which may adversely affect the integrity of the circuits making the integrated chip. Another drawback resides in the added requirement of process alterations necessitated by the presence of certain refractory metals which tend to increase the cost of the product, rendering them uneconomical. Yet a further drawback resides in the presence of conductive paths provided by the presence of portions of barrier metal which may, under certain circumstances, alter the electrical characteristics of the circuits forming the IC chip. Finally, the introduction of a metallic crack stop between fuse links as described by Gilmour et al. will also not work at tight pitches, since the crack stop itself will be ablated by the laser, causing damage to fuses or circuit elements next to it.
Accordingly, it is an object of the invention to provide an improved fuse structure and method for fabricating integrated circuits having laser fuse links.
It is another object of the invention to provide an improved fuse structure and a method therefor, which advantageously allows more fuses to be concentrated into a given space by reducing the distance (pitch) between adjacent fuses.
It is still another object to prevent either the energy inherent of a laser beam or the damage caused by the fuse blowing, to reach or affect any adjacent fuse links or circuit elements in the immediate vicinity of the fuse link being programmed.
It is a further object to protect fuse links which span over several wiring layers when at least some of the fuse links within the structure are programmed by a laser beam.
In one aspect of the invention, the damage done to areas surrounding fuses packed closely together is limited by creating material discontinuities in the form of voids between fuses which will act as crack arresting structures. These xe2x80x9ccrack stopsxe2x80x9d can then be used in various configurations to contain the extent of damage around a blown fuse.
In another aspect of the invention, an integrated circuit is designed to include additional structures characterized by the absence of material, and placed between fuses and parallel to the fuses. The laser fuse link is configured to be set by a laser beam during fabrication of the integrated circuit.
In yet another aspect of the invention, these crack stops are positioned immediately surrounding the region of the fuses blown on a fuse link.
In one embodiment of the invention, there is provided a fuse structure including: an insulated semiconductor substrate; a fuse bank integral to the insulated semiconductor substrate consisting of a plurality of parallel co-planar fuse links; and voids interspersed between each pair of the fuse links, the voids extending beyond a plane defined by the co-planar fuse links.
In another embodiment of the invention, there is provided a fuse structure integral to a semiconductor substrate including: a fuse bank integral to the semiconductor substrate and consisting of a plurality of co-planar fuse links, each of the fuse links being provided with a co-planar area extending beyond the width of the fuse link; and voids positioned within the semiconductor substrate and interspersed between each pair of the fuse links surrounding the co-planar areas.
In a third embodiment of the invention there is provided a fuse structure integral to a semiconductor substrate providing support to a plurality of stacked insulated wiring layers including: integral to a first one of the stacked insulated wiring layers, a fuse bank comprising at least two co-planar rows of fuse links; integral to a second one of the stacked insulated wiring layers, a conducting bus positioned in a direction transversal to the direction of at least the two rows of fuse links; and portions of conductive material placed between the at least two rows of fuse links and running in a direction parallel to the bus.
In another aspect of the invention, there is provided a method of forming a fuse structure integral to a semiconductor substrate supporting a plurality of stacked insulated wiring layers which includes the steps of: providing to a first one of the stacked insulated wiring layers a fuse bank comprising at least two co-planar rows of fuse links; providing to a second one of the stacked insulated wiring layers, a conducting bus positioned in a direction transversal to the direction of the at least two row of fuse links; and placing portions of conductive material between the at least two rows of fuse links and running in a direction parallel to the bus.